Luigi Capodieci, Ph.D. - CTO
Dr. Luigi Capodieci oversees Motivo’s technology development and strategy. He has worked on lithographic imaging, patterning and process simulations for more than 20 years, with applications to Optical Proximity Correction, Phase Shift Masks, Resolution Enhancement Technology and Design/Process Co-Optimization. At Advanced Micro Devices, Inc. (AMD), he pioneered the field of Design For Manufacturability (DFM) integrating physical design CAD flows with rigorous layout printability process modeling and novel verification algorithms. After serving as Director of DFM/CAD at GLOBALFOUNDRIES since that company's inception, Dr. Capodieci was elected Engineering Fellow in 2015 and became responsible for Design Enablement and DFM technology strategy for all the advanced nodes.
He holds a Doctor degree in Electronic Engineering and Computer Science from the University of Bologna, Italy and a Ph.D. in Electrical Engineering, from the University of Wisconsin-Madison, where he worked at the Center for Nanotechnology (CNTech, formerly Center for X-Ray Lithography). He has authored and co-authored more than 70 journal and conference technical publications and is the principal inventor or co-inventor in 40 U.S. Patents. He is an active member of the IEEE and ACM technical organizations and serves as the Chair of the DFM Conference at the SPIE Advanced Lithography Symposium. In 2015 he was elected to the rank of SPIE Fellow in Applied Optical Science and Photonics, a major recognition from the technical and professional community.
Dr. Capodieci pioneered the introduction of machine learning tools and neural network computations for VLSI CAD and IC Semiconductor Process Manufacturing in 1996 and has maintained and expanded his technical vision into today’s current “deep learning and AI renaissance.”
His work in this field includes, notably:
Ph.D. Dissertation, “Introducing a novel technique based on neural networks for the extraction and optimization of process parameters: "Optimization Techniques for VLSI Process Modeling and TCAD in Semiconductor Manufacturing"
http://books.google.com/books?id=L5dpAAAAMAAJ&q=neural+network
Patent: US6272392: "Methodology for extracting effective lens aberrations using a neural network” http://www.google.ch/patents/US6272392
Peer-reviewed technical journal articles:
“Novel methodology for postexposure bake calibration and optimization based on electrical linewidth measurement and process metamodeling (using neural networks)”; JVST-B: http://scitation.aip.org/content/avs/journal/jvstb/16/6/10.1116/1.590402;
Technical Publication (September 2016):
Data analytics and machine learning for continued semiconductor scaling (spie.org/newsroom/6702-data-analytics-and-machine-learning-for-continued-semiconductor-scaling)